Electronic systems typically require one or more regulated voltages to power various subsystems. A regulator is a circuit that may receive an input voltage and produce a regulated output voltage that may be at a different voltage level than the input voltage. One common type of regulator circuit is a low dropout regulator (“LDO”). An LDO regulator is a DC linear voltage regulator which can regulate the output voltage even when the input (or supply) voltage is close to the output voltage.
Switched-mode chargers, linear battery chargers, buck/boost regulators, and other related power charging devices include an onboard LDO circuit configured to supply power to the low side and high side of power transistor drivers. Such an LDO regulator circuit usually includes multiple input power sources. For a single-input charger, the LDO regulator usually has two power sources such as universal serial bus (“USB”) input power source and battery input power source. Whereas for a dual-input charger, the LDO regulator usually has three power sources such as USB, direct current (“DC”), and battery power sources.
To support multiple input power sources, LDO regulators include selection logic configured for selecting an active power path from among the multiple power paths of the input power sources, and for preventing back power leakage from the active power path into the inactive power paths. The LDO regulator should therefore be adapted to select and power up from each of the multiple input power sources, and also to isolate the multiple power sources from one another to prevent back power leakage.
Conventionally this multiple input power path selection option is addressed using an input power multiplexer (“MUX”) in the LDO regulator as the selection logic to select the input power source (e.g., USB, DC, or battery) that will supply power to the LDO regulator output. The MUX selection logic configuration requires two or more power transistors in the series in the power path from the input power source to the output of the LDO regulator. Power transistors are generally large due to the fact that they conduct power from the power source to the output of the LDO regulator circuit. Having multiple transistors in series in the power path is therefore expensive in terms of integrated circuit device area.
FIG. 1 depicts an example circuit diagram of a conventional LDO regulator circuit configuration using MUX selection logic in the power path. In the figure circuit 10 includes a power MUX 101 coupled with a LDO regulator circuit 120. Notably there are two or more power transistors in series in each of the power paths from the input power sources to the output LDO_Out of the LDO regulator circuit.
The power MUX 101 includes a power P-type Field Effect Transistor (“PFET”) 102 in the first power path from the first power source PWR_SRC1 (USB) to LDO_Out. An enable signal EN_Path1 is received at the gate terminal of PFET 102 via an inverter circuit 105 to activate or deactivate the power PFET 102 in the first power path based on the polarity of the enable signal EN_Path1. Power MUX 101 further includes two power PFETs 104 and 106 in series in the second power path from the second power source PWR_SRC2 (Battery) to LDO_Out. An enable signal EN_Path2 is received at the gate terminal of power PFETs 104 and 106 via an inverter circuit 107 to activate or deactivate the power PFETs 104 and 106 in the second power path based on the polarity of the enable signal EN_Path2.
In addition, PFETs 102, 104 and 106 are further connected in series with PFET 108 in the LDO regulator 120 in the first and second power paths, respectively. The PFET 108 is activated and deactivated by operational amplifier 110 in the LDO regulator 120. Thus in the conventional configuration of circuit 10, there are two power PFETs 102 and 108 connected in series in the first power path and three power PFETs 104, 106 and 108 connected in series in the second power path.
Power transistors are required to conduct power from the power source to the output of the LDO regulator. The device size of power transistors must therefore be large to accommodate conducting power in the circuit. Additionally PFETs are typically larger in size than N-type Field Effect Transistors (“NFETs”). Minimizing the number and size of the power transistors in the power path is therefore desirable in order to decrease the overall cost of the LDO regulator circuit in terms of integrated circuit device area.